1. Field of the Invention
The present invention relates to electronic memory devices, and more particularly, to non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof.
2. Description of the Related Art
Non-volatile floating gate memories, such as silicon-oxide-nitride-oxide-silicon (SONOS) flash memories has a attracted attention due to the numerous significant advantages they provide such as non-volatility, excellent scalability, electrical program/erase capability, high density, low power consumption, potential dual-bit-per-cell operation mode, and shock resistance. There are still some efficiency and reliability issues remaining, however, such as poor charge-trapping efficiency and short retention, before related technologies can be exploited.
FIG. 1 is a cross-section of a conventional SONOS memory cell fabricated by a standard CMOS process on a single crystalline silicon substrate. A tunnel oxide layer 12 is formed on a substrate 10 by dry oxidation. A silicon nitride layer 14 is formed on the tunnel oxide layer 12 by a low-pressure chemical vapor deposition (LPCVD). A blocking oxide layer 16 is formed on the silicon nitride layer 14 by LPCVD TEOS. A control gate 20 is formed on the blocking oxide layer 16. Source/drain regions 22 and 24, a passivation layer, contact hole formation and the rest of the process follow a standard MOSFET procedure in order.
Bi-directional read/program non-volatile memory cells capable of storing a plurality of bits in a single cell are also well known in the art. U.S. Pat. No. 6,011,725, the entirety of which is hereby incorporated by reference, discloses a two bit non-volatile electrically erasable and programmable semiconductor memory cell. FIG. 2, a cross-section of a conventional two bit non-volatile electrically erasable and programmable semiconductor memory cell, shows an area of charge trapping under the gate 60 for both the right and the left bits 55a and 55b. An insulating trapping material 54, such as silicon nitride, is typically disposed between two other insulation layers 52 and 56, such as silicon dioxide, to trap charges. The charges are trapped near the source/drain 70 and 80 also to control the conduction of charges in a channel of a transistor. The cell is read in one direction to determine the state of charges trapped near one of the source/drain regions, and is read in the opposite direction to determine the state of charges trapped near the other source/drain region. Hence, these cells are read and programmed bi-directionally. Since the programming and erasing charges are injected into a non-conductive trapping material, the charges do not move as in a conductive material. Moreover, as the channel length shrinks, the charge trapping area may punch through, causing unreliable device performance.
In an article entitled “Quantum-well Memory Device (QWMD) with Extremely Good Charge Retention” by Z. Krivokapic et al., published by IEEE in 2002, the authors disclose a memory device using floating gates as quantum wells. This memory device, however, is very different from a conventional non-volatile memory cell with spaced apart regions and a channel therebetween for the conduction of charges.
FIGS. 3A-3E are cross-sections of fabrication steps for a conventional bi-directional non-volatile memory cells using polysilicon dots as trapping charge materials. Referring to FIG. 3A, a gate oxide layer 110 is formed on a semiconductor substrate 100 by dry oxidation. A polysilicon silicon layer 120 is formed on the gate oxide layer 110 by chemical vapor deposition (CVD). An implantation procedure is then performed to form heavily doped N type Source/drain regions 122 and 124 in areas not covered by polysilicon gate structure 120.
Referring to FIG. 3B, an isotropic etching such as wet etching is performed by dipping in an HF solution. A portion of gate oxide at the edge of the gate structure is etched, creating a gap 115.
Referring to FIG. 3C, a thin silicon oxide layer 130, obtained using rapid process oxidation (RPO) or via LPCVD or PECVD procedures, at a thickness between about 300 to 400 Å, is conformably formed on the surface of polysilicon layer 120 and the semiconductor substrate 100.
Referring to FIG. 3D, a second polysilicon layer 140 is formed on the substrate 100 filling the gap 115. The second polysilicon 140 can be doped in situ, during deposition, via the addition of arsine, or phosphine, to a silane ambient, or the polysilicon layer can be deposited intrinsically then doped via implantation of arsenic or phosphorous ions.
Referring to FIG. 3E, an annealing cycle, performed using conventional furnace procedures or using a rapid thermal annealing procedure at a temperature between about 650 to 800° C., to form a silicon oxide layer 140′ and leave un-reacted polysilicon dots in each gap between the polysilicon gate 120 and the semiconductor substrate 100.
The annealing procedure is critical to controlling oxidation of the polysilicon layer 140. The un-reacted polysilicon dots 140a and 140b may be affected by temperature and duration of the annealing procedure. Moreover, the conventional method requires an additional etching to form a gap 115. The dimension of the gap 115 is difficult to control as channel length of the memory cell shrinks, complicating related processes. Moreover, as the channel length shrinks, the poly dots 140a and 140b are difficult to separate, thereby the memory cell structure is intricate.